The present invention generally relates to the testing and verification of integrated circuits, and more particularly to a method of verifying the operation of programmable logic devices having a sum-of-product (AND/OR) architecture.
Programmable logic devices (PLDs), sometimes referred to as programmable logic arrays (PLAs), used to implement complex logic functions are well known in the art. An example flash erasable reprogrammable CMOS PLD having a sum-of-product (AND/OR) gate array and programmable macrocell logic structure is sold under the designation PALCE20V8 by Advanced Micro Devices, Inc., One AMD Place, P.O. Box 3453, Sunnyvale, Calif. 94088.
For many PLDs, logic equations are programmed into the PLD through floating gate cells in an AND logic array. In the past, verification of device operation has been carried out using a parametric test known as bulk programming or bulk testing. Bulk programming generally involves programming each cell at the same time and then verifying that the device (i.e., the device under test, or DUT) did indeed become programmed as desired, thereby attempting to ensure cell storage.
However, it has recently been determined that many PLDs that fail the bulk programming verification scheme are in fact fully operational devices. In other words, bulk programming results in a fairly high false negative rate. As a result, bulk programming tests unnecessarily can lead to low product yields and/or product lots being held for further analysis.
Accordingly, there exists a need in the art for a testing routine for PLDs that reduces the number of false negative verification results.
According to one aspect of the invention, the invention is a method of testing programmability of a programmable logic device (PLD) having a programmable AND array. The method includes the steps of bulk programming a bulk test pattern across each cell of a cell matrix of the AND array; reading the bulk test pattern;
accepting the programmability test of the PLD if the read bulk test pattern matches an expected result, otherwise: programming a row-by-row test pattern across each cell of the cell matrix of the AND array one row at a time; reading the row-by-row test pattern; and accepting the programmability test of the PLD if the read row-by-row test pattern matches an expected result, and otherwise rejecting the PLD.
According to another aspect of the invention, the invention is a test apparatus for testing programmability of a programmable logic device (PLD) having a programmable AND array. The apparatus includes an interface for receiving and establishing electrical connection to contacts of the PLD; and a processor for executing logic. The logic includes logic to bulk program a bulk test pattern across each cell of a cell matrix of the AND array; logic to read the bulk test pattern; and logic to accept the programmability test of the PLD if the read bulk test pattern matches an expected result, otherwise logic to program a row-by-row test pattern across each cell of the cell matrix of the AND array one row at a time; logic to read the row-by-row test pattern; and logic to accept the programmability test of the PLD of the read row-by-row test pattern matches an expected result, and otherwise rejecting the PLD.